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AL422B Data Sheets
(Revision V1.3)
AL422B
Amendments (Since April 2, 1999)
05-13-99 07-02-99 08-03-99 09-02-99 10-26-99 12-15-99 01-18-01 DC/AC characteristics (including current consumption) updated. Pinout diagram (5.0) and DC external load (7.4) modified. Description about TST pin added in sections 6.0 & 8.1. 8.3.2 Rewritten. Capacitance provided in the AC characteristics section. Remove TST pin restriction. 1. Revised section "8.3.2 Read Enable during Reset Cycles" to "8.3.2 The Proper Manipulation of FIFO Access". 2. Add section "8.3.3 Single Field Write with Multiple Read Operation" 3. Add section "8.3.4 One Field Delay Line (The Old Data Read)" 02-28-02 03-20-02 02-20-03 Address and version update Correct Pin-out diagram Company Contact Information updated
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AL422B 3M-Bits FIFO Field Memory
Contents:
1.0 Description _________________________________________________________________ 4 2.0 Features____________________________________________________________________ 4 3.0 Applications_________________________________________________________________ 4 4.0 Ordering Information _________________________________________________________ 4 5.0 Pinout Diagram______________________________________________________________ 5 6.0 Pin Description ______________________________________________________________ 5 7.0 Electrical Characteristics ______________________________________________________ 6
7.1 Absolute Maximum Ratings ________________________________________________________ 6 7.2 Recommended Operating Conditions ________________________________________________ 6 7.3 DC Characteristics ________________________________________________________________ 6 7.4 AC Characteristics ________________________________________________________________ 7 7.5 Timing Diagrams _________________________________________________________________ 9
8.0 Functional Description_______________________________________________________ 13
8.1 Memory Operation_______________________________________________________________ 14 8.2 Pin 19 Connection _______________________________________________________________ 15 8.3 Application Notes ________________________________________________________________ 15
8.3.1 Irregular Read/Write ___________________________________________________________________ 15 8.3.2 The Proper Manipulation of FIFO Access __________________________________________________ 16 8.3.3 Single Field Write with Multiple Read Operation ____________________________________________ 17 8.3.4 One Field Delay Line (The Old Data Read) _________________________________________________ 17
9.0 Mechanical Drawing ________________________________________________________ 19
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1.0 Description
The AL422B consists of 3M-bits of DRAM, and is configured as 393,216 words x 8 bit FIFO (first in first out). The interface is very user-friendly since all complicated DRAM operations are already managed by the internal DRAM controller. Current sources of similar memory (field memory) in the market provide limited memory size which is only enough for holding one TV field, but not enough to hold a whole PC video frame which normally contains 640x480 or 720x480 bytes. The AverLogic AL422B provides 50% more memory to support high resolution for digital PC graphics or video applications. The 50% increase in speed also expands the range of applications.
2.0 Features
* * * * * * * * * * 384K (393,216) x 8 bits FIFO organization Support VGA, CCIR, NTSC, PAL and HDTV resolutions Independent read/write operations (different I/O data rates acceptable) High speed asynchronous serial access Read/write cycle time: 20ns Access time: 15ns Output enable control (data skipping) Self refresh 3.3V power supply with 5V signal input tolerant Standard 28-pin SOP package
3.0 Applications
* * * * * * * * * Multimedia systems Video capture systems Video editing systems Scan rate converters TV's picture in picture feature Time base correction (TBC) Frame synchronizer Digital video camera Buffer for communications systems
4.0 Ordering Information
Part number AL422B Package 28-pin plastic SOP Power Supply +3.3 volt Status Shipping
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5.0 Pin-Out Diagram
/RRST GND RCK DEC DO1 DO2 DO3 DO4 DO5 DO6
16
28
27
26
25
24
22
21
20
19
18
17
AVERLOGIC AL422B XXXXX XXXX
10 11 12 13 14 1 2 3 4 5 6 7 8 9
15
23
DO7
DO0
/OE
/RE
Lot Number Date Code
GND
WCK
VDD
DI0
DI1
DI2
DI3
DI4
DI5
DI6
TST
/WE
6.0 Pin Description
Pin name DI0~DI7 WCK /WE /WRST DO0~DO7 RCK /RE /RRST /OE TST VDD DEC/VDD GND Pin # 1~4, 11~14 9 5 8 15~18, 25~28 20 24 21 22 7 10 19 6, 23 I/O type input Input Input (active low) Input (active low) Output (tristate) Input Input (active low) Input (active low) Input (active low) Input Function Data input Write clock Write enable Write reset Data output Read clock Read enable Read reset Output enable Test pin (pulled-down)* 3.3V Decoupling cap input Ground
/WRST
DI7
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7.0 Electrical Characteristics
7.1 Absolute Maximum Ratings
Parameter VDD VP IO TAMB Tstg Supply Voltage Pin Voltage Output Current Ambient Op. Temperature Storage temperature Ratings (3.3V) -1.0 ~ +4.5 -1.0 ~ +5.5 -20 ~ +20 0 ~ +70 -55 ~ +125 Unit V V mA C C
7.2 Recommended Operating Conditions
Parameter Min VDD VIH VIL Supply Voltage High Level Input Voltage Low Level Input Voltage +3.0 +2.0 -1.0 3.3V application Max +3.6 +5.5 +0.8 V V V Unit
7.3 DC Characteristics
(VDD = 3.3V, Vss=0V. TAMB = 0 to 70C)
Parameter Min IDD IDD IDD IDD IDDS VOH VOL ILI ILO Operating Current @20MHz Operating Current @30MHz Operating Current @40MHz Operating Current @50MHz Standby Current Hi-level Output Voltage Lo-level Output Voltage Input Leakage Current Output Leakage Current 0.7VDD -10 -10 3.3V application Typ 33 45 57 68 7 Max VDD +0.4 +10 +10 mA mA mA mA mA V V A A Unit
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7.4 AC Characteristics
(VDD = 3.3V, Vss=0V, TAMB = 0 to 70C)
Parameter TWC TWPH TWPL TRC TRPH TRPL TAC TOH THZ TLZ TWRS TWRH TRRS TRRH TDS TDH TWES TWEH TWPW TRES TREH TRPW TOES TOEH TOPW TTR CI CO WCK Cycle Time WCK High Pulse Width WCK Low Pulse Width RCK Cycle Time RCK High Pulse Width RCK Low Pulse Width Access Time Output Hold Time Output High-Z Setup Time Output Low-Z Setup Time /WRST Setup Time /WRST Hold Time /RRST Setup Time /RRST Hold Time Input Data Setup Time Input Data Hold Time /WE Setup Time /WE Hold Time /WE Pulse Width /RE Setup Time /RE Hold Time /RE Pulse Width /OE Setup Time /OE Hold Time /OE Pulse Width Transition Time Input Capacitance Output Capacitance 20 7 7 20 7 7 4 3 3 5 2 5 2 5 2 5 2 10 5 2 10 5 2 10 2 3.3V application Min Max 1000 1000 15 15 15 20 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF Unit
*
Input voltage levels are defined as VIH=3.0V and VIL=0.4V.
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*
The read address needs to be at least 128 cycles after the write address.
DO external load:
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7.5 Timing Diagrams
Reset cycle (s)
cycle n
cycle 0
cycle 1
WCK
TTR TWRS TWRH
/WRST
TDS
TDH
DI7~0 /WE = "L"
n-1
n
0
1
AL422-05 Write Cycle Timing (Write Reset)
cycle n TRPL
Reset cycle (s)
cycle 0
cycle 1
RCK
TRPH
TRRS
TRRH
/RRST
TAC TOH
DO7~0
n-1
n
0
0
1
/RE = /OE = "L" AL422-07 Read Cycle Timing (Read Reset)
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cycle n TRPL
cycle n+1
Disable cycle (s)
cycle n+2
RCK
TRPH TRC TRES TREH
/RE
TRPW TAC TOH
DO7~0 /OE = "L"
n-1
n
n+1
n+2
AL422-08 Read Cycle Timing (Read Enable)
cycle n TRPL
cycle n+1
cycle n+2
cycle n+3
cycle n+4
RCK
TRPH TRC TOES TOEH
/OE
TOPW TAC TOH THZ Hi-Z TLZ
DO7~0 /RE = "L"
n-1
n
n+1
n+4
AL422-09 Read Cycle Timing (Output Enable)
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cycle n TWPL
cycle n+1
Disable cycle (s)
cycle n+2
WCK
TWPH TWC TWES TWEH
/WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
n+2
AL422-06 Write Cycle Timing (Write Enable)
cycle n TRPL
cycle n+1
Disable cycle (s)
cycle 0
RCK
TRPH TRC TRRS TRRH
/RRST
TRES
TREH
/RE
TRPW TAC TOH
DO7~0 /OE = "L"
n-1
n
n+1
0
AL422-14 Read Cycle Timing (RE, RRST)
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cycle n TWPL
cycle n+1
Disable cycle (s)
cycle 0
cycle 1
WCK
TWPH
TWC
TWRS
TWRH
/WRST
TWES
TWEH
/WE
TWPW TDS TDH
DI7~0
n-1
n
n+1
0
1
AL422-15 Write Cycle Timing (WE, WRST)
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8.0 Functional Description
The AL422B is a video frame buffer consisting of DRAM that works like a FIFO which is long enough to hold up to 819x480 bytes of picture information and fast enough to operate at 50MHz. The functional block diagram is as follows:
SRAM Cache Write Data Register Read Data Register
DI7~ DI0
Input Buffer
384k x8 Memory Cell Array
Output Buffer
DO7~ DO0 /OE
WCK /WRST /WE
Write Address Counter
Timing Generator & Arbiter
Read Address Counter
RCK /RRST /RE
Refresh Address Counter
AL422-03 Block Diagram
The I/O pinouts and functions are described as follows: DI7~DI0 Data Input: Data is input on the rising edge of the cycle of WCK when /WE is pulled low
(enabled).
DO7~DO0 Data Output: Data output is synchronized with the RCK clock. Data is obtained at the rising edge of the RCK clock when /RE is pulled low. The access time is defined from the rising edge of the RCK cycle. WCK Write Clock Input: The write data input is synchronized with this clock. Write data is input at the rising edge of the WCK cycle when /WE is pulled low (enabled). The internal write address pointer is incremented automatically with this clock input. RCK Read Clock Input: The read data output is synchronized with this clock. Read data output at the rising edge of the RCK cycle when /OE is pulled low (enabled). The internal read address pointer is incremented with this clock input. /WE Write Enable Input: /WE controls the enabling/disabling of the data input. When /WE is pulled low, input data is acquired at the rising edge of the WCK cycle. When /WE is pulled high, the memory does not accept data input. The write address pointer is stopped at the current position. /WE signal is fetched at the rising edge of the WCK cycle.
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/RE Read Enable Input: /RE controls the operation of the data output. When /RE is pulled low, output data is provided at the rising edge of the RCK cycle and the internal read address is incremented automatically. /RE signal is fetched at the rising edge of the RCK cycle. /OE Output Enable Input: /OE controls the enabling/disabling of the data output. When /OE is pulled low, output data is provided at the rising edge of the RCK cycle. When /OE is pulled high, data output is disabled and the output pins remain at high impedance status. /OE signal is fetched at the rising edge of RCK cycle. /WRST Write Reset Input: This reset signal initializes the write address to 0, and is fetched at the rising edge of the WCK input cycle. /RRST Write Reset Input: This reset signal initializes the read address to 0, and is fetched at the rising edge of the RCK input cycle. TST Test Pin: For testing purpose only. It should be pulled low for normal applications. DEC: Decoupling cap pin, the DEC pin connects to the 3.3V power with regular 0.1F bypass capacitor.
8.1 Memory Operation
Initialization Apply /WRST and /RRST 0.1ms after power on, then follow the following instructions for normal operation. Reset Operation The reset signal can be given at any time regardless of the /WE, /RE and /OE status, however, they still need to meet the setup time and hold time requirements with reference to the clock input. When the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are enabled again. When /WRST signal is pulled low, the data input address will be set to 0 and the data in the Input Buffer will be flushed into memory cell array. When /RRST signal is pulled low, the data output address will be set to 0 and pre-fetch the data from memory cell array to Output Buffer. Write Operation Data input DI7~DI0 is written into the write register at the WCK input when /WE is pulled low. The write data should meet the setup time and hold time requirements with reference to the WCK input cycle.
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Write operation is prohibited when /WE is pulled high, and the write address pointer is stopped at the current position. The write address starts from there when the /WE is pulled low again. The /WE signal needs to meet the setup time and hold time requirements with reference to the WCK input cycle. Read Operation Data output DO7~DO0 is written into the read register at the RCK input when both /RE and /OE are pulled low. The output data is ready after TAC (access time) from the rising edge of the RCK input cycle. The read address pointer is stopped at the current position when /RE is pulled high, and starts there when /RE is pulled low again. /OE needs to be pulled low for read operations. When /OE is pulled high, the data outputs will be at high impedance stage. The read address pointer still increases synchronously with RCK regardless of the /OE status. The /RE and /OE signals need to meet the setup time and hold time requirements with reference to the RCK input cycle. When the new data is read, the read address should be between 128 to 393,247 cycles after the write address, otherwise the output may not be new data.
8.2 Pin 19 Connection
The 3.3V configuration (direct replacement of the previous AL422V3) is as follows:
3.3V 3.3V
AL422B
10 0.1uF VDD DEC 19 0.1uF
8.3 Application Notes
8.3.1 Irregular Read/Write It is recommended that the WCK and RCK are kept running at least 1MHz at all times. The faster one of WCK and RCK is used as the DRAM refresh timing clock and has to be kept free running. When irregular FIFO I/O control is needed, keep the clock free running and use /WE or /RE to control the I/O as follows:
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WCK
Data
/WE
AL422-17 Slow Write - Correct
The following drawing shows irregular clock and should be avoided:
WCK
Data
/WE
AL422-16 Slow Write - Incorrect
8.3.2 The Proper Manipulation of FIFO Access The FIFO memory is designed to allow easy field delay, time-base conversion, and other types of signal processing. To ensure the expectant data can be read out from the AL422B FIFO, the proper manipulation on the AL422B FIFO memory is highly recommended 1. The read address should be between 128 to 393,247 cycles after the write address to read the current field data. (The restriction is indicated in the "Read Operation" Section). 2. The proper FIFO access must make sure after read reset, the read operation will either read all the old data (last field data) until next read reset, or follow the constraint 1 above to read newly update data. In any 2 read resets interval, the FIFO access can not read old data (the field data are written before last write reset), and stop for a period then read the newly update data (even at that time, write counter is ahead of read counter by more than 128 cycles). If the FIFO memory manipulations violate the above conditions, some amount of consecutive unexpected data (old data) will be read at the FIFO data bus.
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8.3.3 Single Field Write with Multiple Read Operation It is one of the functions for FIFO memory that can buffer a field data and do multiple times of fields read access. In some applications, such as still image capturing, require one field write and multiple field data read operations. In order not to violate the 128 cycles of write to read delay latency rule, the write address (pointer) needs to be reset to 0 for the coming multiple read operations so that FIFO can provide the expectant data at DO bus. 8.3.4 One Field Delay Line (The Old Data Read) As the design shown in diagram by applying the reset every 1-field cycle (with the common signal for /WRST and /RRST) and a constant read/write operation (with all /WE, /RE and /OE are tied to ground), "1 field delay line" timing is shown in timing chart below. When the difference between the write address and the read address is 0 (the read address and the write address are the same), the old field data are read as shown in the timing chart.
Reset
AL422
/WRST 8-bit Input DI[7:0] /RRST DO[7:0] /OE /RE RCK Clock 8-bit Output
/WE
WCK
AL422 1 Field Delay Line Diagram
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Field m cycle 0 cycle 1 cycle n cycle 0
Field m + 1 cycle 1
RCK WCK
/RRST /WRST DI7~0
0
1
n
0
1
tAC
DO7~0
0 Data of field m
1
AL422-08 1 Field Delay Line Timing Diagram
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9.0 Mechanical Drawing
28 PIN PLASTIC SOP:
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CONTACT INFORMATION
Averlogic Technologies Corp. 4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan Tel: +886 2-27915050 Fax: +886 2-27912132 E-mail: sales@averlogic.com.tw URL: http://www.averlogic.com.tw
Averlogic Technologies, Inc. 90 Great Oaks Blvd. #204, San Jose, CA 95119 USA Tel: 1 408 361-0400 Fax: 1 408 361-0404 E-mail: sales@averlogic.com URL: http://www.averlogic.com

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